ATA8742-PXQW【PDF 70/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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9151AINDCO07/09

ATA8742

" Bit 4 PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-

rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

18.2.3

GIFR General Interrupt Flag Register

" Bits 7, 3..0 Res: Reserved Bits

These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.

" Bit 6 INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

" Bit 5 PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT11..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

" Bit 4 PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF becomes set

(one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

18.2.4

PCMSK1 Pin Change Mask Register 1

" Bits 7, 4 Res: Reserved Bits

These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.

" Bits 3..0 PCINT11..8: Pin Change Enable Mask 11..8

Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on

Bit

0x3A (0x5A

INTF0

PCIF1

PCIF0

GIFR

Read/Write

R/W

Initial Value

Bit

0x20 (0x40)

PCINT11

PCINT10

PCINT9

PCINT8

PCMSK1

Read/Write

R/W

Initial Value

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